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VERDOSCIA, LORENZO

VERDOSCIA, LORENZO  

Istituto di Calcolo e Reti ad Alte Prestazioni - ICAR  

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Titolo Data di pubblicazione Autore(i) File
A Data-Flow Methodology for Accelerating FFT 1-gen-2019 Verdoscia, Lorenzo; I, Amin Saheb; Giorgi, Roberto
A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs 1-gen-2016 Verdoscia L.; Giorgi R.
A clockless computing system based on the static dataflow paradigm 1-gen-2014 Verdoscia, L; Vaccaro, R; Giorgi, R
Position paper: Validity of the static dataflow approach for exascale computing challenges 1-gen-2013 Verdoscia, Lorenzo; Vaccaro, Roberto
D 3 AS project: a different approach to the manycore challenges 1-gen-2012 Lorenzo Verdoscia; Roberto Vaccaro
CODACS project: A Development Tool for Embedded System Prototyping 1-gen-2004 Verdoscia Lorenzo
CODACS Prototype: CHIARA Language and its Compiler 1-gen-2004 Verdoscia, Lorenzo; Danelutto, Marco; Esposito, Raffaele
CODACS Project: Level-Node Communication Policies 1-gen-2003 Verdoscia, L; Scafuri, U
HCRC- parallel computer Architecture: Reason for a choice 1-gen-1986 Giordano, A; Iazzetta, A; I Noviello, E; Scafuri, U; Vaccaro, R; Verdoscia, L; Villano, U