VLSI architecture of a multi-standard videocoder

Aim of this work is to propose a possible VLSi architecture of a real-time videocoder for different resolution formats (CCIR-601/SIF). This videocoder is based on hybrid predictive algorithms (block mode operations) and it is suitable for multi-media communications for ATM networks up to 10 Mb/s. The most important feature is down-compatibility respect to previously defined low-speed standard (up to 1.5 Mb/s). The coding/decoding algorithm scheme reviewed in this paper is still in the developing phase and it may be modified to achive better performances. The proposed hardware approach is based on the pipeline architecture, with several independent processing units working in parallel. Shared memory arrays are exploited to interconnect different units with no speed degradation. Moreover, to match real-time specifications and reduce I/O bottlenecks, each element has its own private working memory, processor and specialized I/O interface. The key point for a fast VLSi implementation of the proposed algorithms is the use of ASIC methodologies (e.g., Standard Cells and/or Sea of Gates). Finally, for each computational units, a functional scheme is proposed alaong with a raw gate count.