Computer-aided synthesis of a Bidimensional Discrete Cosine Transform chip

This paper describes the design of an integrated circuit implementing a Bidimensional Discrete Cosine Transform (BDCT). Such a circuit may be used to reduce redundancy of video information in low bit-rate transmission channels and video compression for image storage and retrieval. The chip architecture is motivated by the consideration that the BDCT equations can be solved row-by-row and column-by-column by a simpler Monodimensional DCT (MDCT). Therefore the chip structure is partitioned into three stages: the first and the last one implement MDCTs while the second stage is a shared memory array. The DCT design was achieved by means of the OLYMPUS synthesis system, an experimental suite of synthesis tools developed at Stanford University. A parametrized behavioral description of the monodimensional DCT operator was specified in a high-level language in terms of concurrent process communicating through a shared medium. The circuit layout was synthesized automatically from this description.