We present the paralle1 implementation of matrix-vector multiplication on a binary tree of a small number of processor, whose leaves are connected to loca1 memories, each containing one column of the matrix. The performance attained can be favourably compared with the one of the mesh of trees and the linear array, each formed by the same number of processors.
A comparison of the performance of three parallel architectures for matrix-vector multiplication
Codenotti B;
1988
Abstract
We present the paralle1 implementation of matrix-vector multiplication on a binary tree of a small number of processor, whose leaves are connected to loca1 memories, each containing one column of the matrix. The performance attained can be favourably compared with the one of the mesh of trees and the linear array, each formed by the same number of processors.File in questo prodotto:
| File | Dimensione | Formato | |
|---|---|---|---|
|
prod_419357-doc_148182.pdf
accesso aperto
Descrizione: A comparison of the performance of three parallel architectures for matrix-vector multiplication
Dimensione
738.91 kB
Formato
Adobe PDF
|
738.91 kB | Adobe PDF | Visualizza/Apri |
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
