Cache architecture for single-chip implementation

The gap between the speed of microprocessors and the access times to cheap memory devices has grown to such extent as to make it worthwhile introducing a cache memory even in microprocessor-based computer organizations. Implanting a cache on more than a single chip is not viable, both to keep the overall cache cost low, and to avoid performance degradation. On the other hand, a single-chip cache implementation presents new problems, such as the limited chip pin-out, and the trade-off between the capacity of the cache and the complexity of the logic for cache management. In this paper, the architecture of a virtual address cache is presented, which solves these problems by means of software control over the operations of the cache.