We study the problem of routing wires in a VLSI 2-dimensional array, with the goal of minimizing the resulting channel width. We develop an experimental environment oriented towards the test of heuristics and the experimental analysis of the average-case channel width needed to route an nxn array. We give a special attention to the role played by the number of turns of the routings.

Global routing in VLSI arrays : an experimental environment

Codenotti B;
1989

Abstract

We study the problem of routing wires in a VLSI 2-dimensional array, with the goal of minimizing the resulting channel width. We develop an experimental environment oriented towards the test of heuristics and the experimental analysis of the average-case channel width needed to route an nxn array. We give a special attention to the role played by the number of turns of the routings.
1989
Istituto di Scienza e Tecnologie dell'Informazione "Alessandro Faedo" - ISTI
Global routing
VLSI array
Pin
Chip
Channel width
Heuristics
Turns
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/377015
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