A comparison-based diagnosis algorithm tolerating comparator faults

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A promising application of system-level diagnosis is the testing of VLSI chips during the manufacturing process. A comparison-based diagnosis is easier to implement on the wafer than the PMC-conform one. However, existing comparison models essentially overlook the test invalidation due to the physical faults in the comparators. This paper proposes a comparison-based model and a diagnosis algorithm which takes into account the effects of faults that affect the comparators. In order to deal with faults in the comparators, a preliminary comparator test session is included. This session requires the adjacent units to be able to feed the comparator with all needed patterns independently of each other. As shown in the paper, this requirement can be satisfied at a relatively small wafer design cost. The test session can also be extended to handle the faults in the syndrome collection circuitry.