The application of bias stress with high source-drain voltage and different gate voltages in polycrystalline silicon thin-film transistors produces marked modifications both in the off current as well as device transconductance. These effects are explained in terms of hot-carrier effects related to a combination of charge injection into the gate insulator and formation of interface states near the drain.
Hot hole-induced degradation in polycrystalline silicon thin film transistors: experimental and theoretical analysis
GTallarida;LMariucci;
1994
Abstract
The application of bias stress with high source-drain voltage and different gate voltages in polycrystalline silicon thin-film transistors produces marked modifications both in the off current as well as device transconductance. These effects are explained in terms of hot-carrier effects related to a combination of charge injection into the gate insulator and formation of interface states near the drain.File in questo prodotto:
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