Grain boundary evaluation in sequentially laterally solidified polycrystalline-silicon devices

A systematic study has been made of the conduction process in polycrystalline-silicon thin film transistors (poly-Si TFTs) using carrier flow parallel and perpendicular to sub-grain-boundaries in sequentially laterally solidified material. The objective of this investigation was to obtain an unambiguous characterization of grain boundary (GB) behavior. By studying orthogonal TFTs in this anisotropic material, it was possible to distinguish grain boundary carrier trapping from intragrain trapping. In conventional poly-Si, the material is isotropic over distances greater than the grain size of similar to 300 nm, and there is no direct and clear-cut way of distinguishing between intragrain and intergrain trapping centers. In the experimental samples, the thermal activation energy of the channel current was measured in the two orthogonal directions, and the difference in activation energy was related to carrier flow over perpendicular sub-GBs. The detailed interpretation of the experimental results was facilitated by two-dimensional numerical simulations, demonstrating that a planar barrier GB, which simply resulted in a potential barrier within the channel, was fundamentally incompatible with the experimental drain current activation energy data. It was only possible to obtain a satisfactory representation of all the experimental data by using a finite width GB, in which carrier flow was controlled by transport across the resistive GB region, rather than by emission over a barrier. This representation of the sub-GB permitted the essential combination of reduced field effect mobility, for orthogonal carrier flow, and a drain current activation energy, which was close to zero.