This project dealt with one of the major issues of concern for the future submicron integrated circuit technology, namely the fabrication of ultra-shallow junctions (< 100 nm) by dopant ion implantation in silicon at different energies (£ 1 keV for B and some keV for BF2 and As) and rapid thermal processing (RTP) and/or spike annealing (SA). The process conditions (implantation energy and dose, substrate temperature and heating parameters) was identified by means of a complete structural, electrical and chemical characterization of the processed material. This was achieved by disposing of a proper combination of sensitive and reliable diagnostic techniques to analyze, before and after annealing, the defect type, size and concentration, the depth distribution of the dopant and its electrically activated amount, and to investigate their effects on the performance of the final device (prototype of the project).

Ion Implantation at Ultra-Low Energy for Future Semiconductor Devices

Servidori M;Milita S;Privitera V;Mannino G;
2004

Abstract

This project dealt with one of the major issues of concern for the future submicron integrated circuit technology, namely the fabrication of ultra-shallow junctions (< 100 nm) by dopant ion implantation in silicon at different energies (£ 1 keV for B and some keV for BF2 and As) and rapid thermal processing (RTP) and/or spike annealing (SA). The process conditions (implantation energy and dose, substrate temperature and heating parameters) was identified by means of a complete structural, electrical and chemical characterization of the processed material. This was achieved by disposing of a proper combination of sensitive and reliable diagnostic techniques to analyze, before and after annealing, the defect type, size and concentration, the depth distribution of the dopant and its electrically activated amount, and to investigate their effects on the performance of the final device (prototype of the project).
2004
Istituto per la Microelettronica e Microsistemi - IMM
low energy implantation
shallow junction
CMOS
profiling techniques
structural characterization
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/183448
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