Electrical characterization of directionally solidified polycrystalline silicon

An investigation has been undertaken of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using sequential laterally solidified material. This material has a location-controlled distribution of grain boundaries (GBs), which makes it particularly useful for the investigation of their influence on the performance of poly-Si TFTs, and to address the issue of the role of spatially localized trapping states. The experimental results showed that the specific location of the GBs had a minimal effect upon TFT performance, and most aspects of TFT performance could be accurately simulated using a spatially uniform distribution of states. The conclusion to arise from this study is that, with the exception of field-effect mobility, there are no features in the device behavior, which must be specifically attributed to the spatial localization of trapping states. A limited comparison with conventional laser-crystallized poly-Si was undertaken, and, in this material, it was found that the effects of trap localization were apparent. (c) 2005 American Institute of Physics.