In this work terbium scandate thin films have been deposited by atomic layer deposition (ALD) on SiO2/Si and Si3N4/SiO2/Si stacks and their structural and electrical behavior as a function of annealing temperature has been investigated. Films were grown using ?-diketonate-based precursors and ozone at 300oC. The film crystallization in the cubic phase is induced as film thickness increases and enhanced by thermal annealing. The thermal stability of ALD TbScOx films and of their interfaces with SiO2 and Si3N4 is preserved after thermal treatment at 600oC, and their electrical characterization shows well-shaped capacitance-voltage curves, from which a k value of 16-18 is extracted. Annealing at 900oC largely affects the TbScOx/SiO2 interface, causing the formation of an intermixed layer and silicon diffusion in the film resulting in a reduction of its k value down to 12. On the contrary TbScOx/Si3N4 stack results stable upon 900oC thermal treatment, indicating the feasibility for terbium scandate integration as high k dielectric in charge trap memory devices.

Structural and electrical properties of terbium scandate films deposited by atomic layer deposition and high temperature annealing effects

Cianci Elena;Lamperti Alessio;Spiga Sabina
2012

Abstract

In this work terbium scandate thin films have been deposited by atomic layer deposition (ALD) on SiO2/Si and Si3N4/SiO2/Si stacks and their structural and electrical behavior as a function of annealing temperature has been investigated. Films were grown using ?-diketonate-based precursors and ozone at 300oC. The film crystallization in the cubic phase is induced as film thickness increases and enhanced by thermal annealing. The thermal stability of ALD TbScOx films and of their interfaces with SiO2 and Si3N4 is preserved after thermal treatment at 600oC, and their electrical characterization shows well-shaped capacitance-voltage curves, from which a k value of 16-18 is extracted. Annealing at 900oC largely affects the TbScOx/SiO2 interface, causing the formation of an intermixed layer and silicon diffusion in the film resulting in a reduction of its k value down to 12. On the contrary TbScOx/Si3N4 stack results stable upon 900oC thermal treatment, indicating the feasibility for terbium scandate integration as high k dielectric in charge trap memory devices.
2012
Istituto per la Microelettronica e Microsistemi - IMM
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/276413
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