Investigation of SiO2/HfO2 gate stacks for application to non-volatile memory devices

Engineering of the tunnel barrier of non-volatile memories is addressed in this paper. The strong potential of multilayer stacks for reducing the programming times of these devices, without altering their retention characteristics, is studied. To this aim, experimental results showing the improved field sensitivity of the gate current of MOS devices with SiO 2/HfO2 gate stacks compared to SiO2 of identical electrical thickness (EOT) are presented. Simulations of the corresponding tunnelling currents are also reported. Our electrical measurements suggest that it is of great interest to investigate the use of SiO 2/HfO2 stacks as tunnel barriers for NVMs. These experimental results on double-layer stacks allow to confirm experimentally a conduction principal that could be used in symmetrical triple-layer SiO 2/high-k/SiO2 tunnel barriers, thus allowing an advantageous behaviour in both conduction directions. Further simulations are presented in order to evaluate the best parameters that the high-k layer should have in order to lead to better performance than a SiO2 tunnel barrier. They suggest that if the high-k has 1.5-2.0 eV conduction band offset compared to Si its relative effective mass and dielectric constant should meet the constraint: ?high-k·mhigh-k>=5 (mhigh-k, relative electron mass; ?high-k, relative dielectric constant).