In this paper we propose a technique to implement in a parallel fashion a turbo decoder based on an arbitrary permutation, and to expand its interleaver in order to produce a family of prunable S-random interleavers suitable for parallel implementations. We show that the spread properties of the obtained interleavers are almost optimal and we prove by simulation that they are very competitive in terms of error floor performance. A few details on the decoder architecture are also provided.

Design of prunable interleavers for parallel turbo decoder architectures

Tarable Alberto;
2007

Abstract

In this paper we propose a technique to implement in a parallel fashion a turbo decoder based on an arbitrary permutation, and to expand its interleaver in order to produce a family of prunable S-random interleavers suitable for parallel implementations. We show that the spread properties of the obtained interleavers are almost optimal and we prove by simulation that they are very competitive in terms of error floor performance. A few details on the decoder architecture are also provided.
2007
Istituto di Elettronica e di Ingegneria dell'Informazione e delle Telecomunicazioni - IEIIT
parallel implementation
prunable interleavers
turbo codes
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/292185
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