We show that the main causes of V(T) variations are the drain induced barrier lowering (DIBL) and floating body effects (FBEs), induced by impact ionization. The relative influence of FBEs and DIBL is analysed by performing numerical simulations with or without including the impact ionization model.

Threshold voltage variations induced by drain bias in short channel polycrystalline silicon thin film transistors

Valletta A;Mariucci L;Cuscuna M;Maiolo L;Simeone D;
2009

Abstract

We show that the main causes of V(T) variations are the drain induced barrier lowering (DIBL) and floating body effects (FBEs), induced by impact ionization. The relative influence of FBEs and DIBL is analysed by performing numerical simulations with or without including the impact ionization model.
2009
Istituto per la Microelettronica e Microsistemi - IMM
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/295144
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