Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM-like and/or eXecuted-in-Place requirements of Storage Class Memory devices. In this paper we design an ECC decoder of a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by precomputing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated based on the number of elementary gates.Eventually, the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3 ns and a total area less than 250 000 umq.
Embedded three-bit ECC for Emerging Memories
2016
Abstract
Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM-like and/or eXecuted-in-Place requirements of Storage Class Memory devices. In this paper we design an ECC decoder of a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by precomputing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated based on the number of elementary gates.Eventually, the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3 ns and a total area less than 250 000 umq.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
