The architecture of a capability-based microprocessor system

We present the results of research aimed at the definition and implementation of a microprocessor-based advanced architecture whose main goal is the reduction of the semanthic gap. This architecture is oriented toward high-level languages supporting modular decomposition of programs, user-defined data abstraction, and concurrency. Its salient features are a capability-oriented addressing scheme, an approach to memory management based on the concept of a single-level store, implementation of tagged storage by the tagging of memory segments, and significant hardware support for multitasking. We present this architecture with particular reference to object types and memory management, and we evaluate it according to how well it reduces the semantic gap. We also show how it has been as a research prototype in which the central processing unit has been built around an off-the-shelf microprocessor and in which an intelligent memory device autonomously supports the memory management functions.