Research on the classification of neutron/gamma waveforms in scintillators using Pulse Shape Discrimination (PSD) techniques is still an active topic. Numerous methods have been explored to optimise this classification. Some of the most recent research is focused on machine learning techniques for this classification with excellent results. In this field, FPGAs with high-sampling rate ADCs have been used to perform this classification in real-time. In this work, we select a potential architecture and implement it with the help of the IntelFPGA OpenCL SDK environment. The shorter and C-like development of OpenCL enables more straightforward modification and optimisation of the network architecture. The main goal of the work is to evaluate the resources and performance of a complete solution in the FPGA. The dataset used to model the neural network is provided by JET. The FPGA design is generated as if it was connected to an ADC module streaming the data samples with the help of a Board Support Package developed for an IntelFPGA ARRIA10 available in an AMC module in an MTCA.4 platform. The prototyped solution has been integrated into EPICS using the Nominal Device Support (NDSv3) model that is currently being developed by ITER.
Real-Time Implementation of the Neutron/Gamma discrimination in an FPGA-based DAQ MTCA platform using a Convolutional Neural Network
Murari Andrea;
2020
Abstract
Research on the classification of neutron/gamma waveforms in scintillators using Pulse Shape Discrimination (PSD) techniques is still an active topic. Numerous methods have been explored to optimise this classification. Some of the most recent research is focused on machine learning techniques for this classification with excellent results. In this field, FPGAs with high-sampling rate ADCs have been used to perform this classification in real-time. In this work, we select a potential architecture and implement it with the help of the IntelFPGA OpenCL SDK environment. The shorter and C-like development of OpenCL enables more straightforward modification and optimisation of the network architecture. The main goal of the work is to evaluate the resources and performance of a complete solution in the FPGA. The dataset used to model the neural network is provided by JET. The FPGA design is generated as if it was connected to an ADC module streaming the data samples with the help of a Board Support Package developed for an IntelFPGA ARRIA10 available in an AMC module in an MTCA.4 platform. The prototyped solution has been integrated into EPICS using the Nominal Device Support (NDSv3) model that is currently being developed by ITER.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


