Repeated modular additions and overflow detection are practicable in Hybrid Number Systems. In this paper, an adding, overflow-detecting procedure is described and evaluated by statistical methods; a circuit is proposed allowing a mean addition time less than 8.9 gate delays for numbers having a magnitude order normally distributed in [-2^33, 2^33-1].
A fast digital circuit for iterative additions in HNS
1994
Abstract
Repeated modular additions and overflow detection are practicable in Hybrid Number Systems. In this paper, an adding, overflow-detecting procedure is described and evaluated by statistical methods; a circuit is proposed allowing a mean addition time less than 8.9 gate delays for numbers having a magnitude order normally distributed in [-2^33, 2^33-1].File in questo prodotto:
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Descrizione: A fast digital circuit for iterative additions in HNS
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