This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infiniteimpulse- response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. A chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to 11 chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-m CMOS technology and has a core area of approximately 19 mm2.

An efficient VLSI architecture for real-time additive synthesis of musical signals

Bertini G
1999

Abstract

This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infiniteimpulse- response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. A chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to 11 chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-m CMOS technology and has a core area of approximately 19 mm2.
1999
Istituto di Scienza e Tecnologie dell'Informazione "Alessandro Faedo" - ISTI
Inglese
7
1
105
110
6
http://www.scopus.com/inward/record.url?eid=2-s2.0-0033099032&partnerID=q2rCbXpz
Additive synthesis
Bit-level systolic arrays
IIR marginally stable filters
Musical synthesis algorithms
Real-time musical synthesis
Sinusoid generation
Systolic architectures
Short papers. IEEE, 1999. - Codice PuMa: cnr.iei/1999-A0-001
1
info:eu-repo/semantics/article
262
De Bernardinis F.; Roncella R.; Saletti R.; Terreni P.; Bertini G.
01 Contributo su Rivista::01.01 Articolo in rivista
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/387929
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