We present a hardware-algorithm for selecting the ?-th smallest item among N elements (for all ranges of N) using a p-classifier device, while strictly enforcing conflict-free memory accesses. Specifically, we show that, by using our design, selection can be accomplished optimally in O(N/p) time. © 1999 Springer-Verlag Berlin Heidelberg.

An optimal hardware-algorithm for selection using a fixed-size parallel classifier device

1999

Abstract

We present a hardware-algorithm for selecting the ?-th smallest item among N elements (for all ranges of N) using a p-classifier device, while strictly enforcing conflict-free memory accesses. Specifically, we show that, by using our design, selection can be accomplished optimally in O(N/p) time. © 1999 Springer-Verlag Berlin Heidelberg.
1999
Istituto di Scienza e Tecnologie dell'Informazione "Alessandro Faedo" - ISTI
Processor architectures. Other architecture styles
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/391708
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