Optimal VLSI structure for high speed pipeline using RNS

Designing computing structures for FFT with ever lower response time has been an attractive goal for several years and many algorithms and architectural solutions have been introduced. Out of the proposed techniques, the use of residue number systems (RNS) proved to be profitable to speed up computations, not only for FFT [1, 2], but for many other problems as well, in the area of digital signal processing (DSP). Actually, additions and multiplications are mainly involved in DSP, with results expected within known ranges; on the other hand, RNS-based arithmetic units are highly efficient just for addition and multiplication, since they are carry-free operations. Moreover RNS allow to design modular and regular structures and therefore are well suited for VLSI implementations, to vantage of area saving. In this work a VLSI structure, based on RNS units, to perform the N point FFT on a continuous data stream is proposed, and its performance is evaluated in terms of asymptotic VLSI complexity.