VLSI systolic arrays for band matrix multiplication

The advent of VLSI technology has deeply modified the design of digitai systems. The structure of special algorithms is now close to the structure of communication and computing resources on the silicon chip. Modular and regular structures allow parallel VLSI algorithms with good figures of complexity in terms of speed and size. In this paper systolic arrays of processors are used to define two new faster VLSI algorithms for solving the problem of multiplying two band matrices. The proposed algorithms are based on different area-time trade-off: they exhibit w_A·W_B processors, n steps and n?2 processors, min{w_A, w_B} steps respectively, compared with w_A·W_B processors, 3n steps of the previously known VLSI algorithm.