This paper presents a synthesis method to realize any p-state normal asynchronous sequential circuit A according to an unconventional structure. It consists of two critical-race free S.T.T. normal asynchronous circuits A1 and A2 connected in series, where A1 is realized with L internal variables and A2 with 2 ¿ So internal variables (So = [ log2 p] ). It is shown that L = 1 for circuit A with single inpunt transitions, and that L is equal to the number of input terminals of A for circuit with multiple input transitions. The internal structure of circuit A2 is investigated by using partition algebra. As a result of this investigation it is shown that A2 can always be realized according to a general model with only So feedback paths, each one including a master-slave flip-flop. Using this model and a straigtforward synthesis procedure, any p-state normal asynchronous circuit can therefore be realized by So + L feed-back Paths.
Synthesis of asynchronous sequential circuits with master- slave subcircuits
1971
Abstract
This paper presents a synthesis method to realize any p-state normal asynchronous sequential circuit A according to an unconventional structure. It consists of two critical-race free S.T.T. normal asynchronous circuits A1 and A2 connected in series, where A1 is realized with L internal variables and A2 with 2 ¿ So internal variables (So = [ log2 p] ). It is shown that L = 1 for circuit A with single inpunt transitions, and that L is equal to the number of input terminals of A for circuit with multiple input transitions. The internal structure of circuit A2 is investigated by using partition algebra. As a result of this investigation it is shown that A2 can always be realized according to a general model with only So feedback paths, each one including a master-slave flip-flop. Using this model and a straigtforward synthesis procedure, any p-state normal asynchronous circuit can therefore be realized by So + L feed-back Paths.| File | Dimensione | Formato | |
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Descrizione: Synthesis of asynchronous sequential circuits with master- slave subcircuits
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