In this paper we present the design of CNTFETs-based ternary logic gates, which are a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. In particular we propose the design of a 3 × 1 Mux and a D flip flop, all in ternary logic. Simulations are performed in Verilog-A, using a CNTFET model already proposed by us. The obtained results are encouraging and show that this approach is suitable for high frequency signals.
Three-levels logic gates design based on CNTFETs
Marani R;
2019
Abstract
In this paper we present the design of CNTFETs-based ternary logic gates, which are a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. In particular we propose the design of a 3 × 1 Mux and a D flip flop, all in ternary logic. Simulations are performed in Verilog-A, using a CNTFET model already proposed by us. The obtained results are encouraging and show that this approach is suitable for high frequency signals.File in questo prodotto:
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