In this paper we propose the design of a novel full adder circuit, based both on CNTFET and CMOS technology, in order to compare them. The proposed full adder circuit is based on NAND and NOT logic gates. For this reason we characterize NAND and NOT gates at different supply voltages and frequencies, for both technologies. The optimal results, obtained using Advanced Design System (ADS), are at 0.5 V and 50 GHz for CNTFET, while for CMOS technology at 3 V and 200 MHz. Moreover we present the comparison between the two considered technologies in term of velocity, delay and power delay product (PDP), showing quantitatively the improvements obtained with CNTFET technology.
Design and simulation study of full adder circuit based on CNTFET and CMOS technology by ADS
Marani R;
2018
Abstract
In this paper we propose the design of a novel full adder circuit, based both on CNTFET and CMOS technology, in order to compare them. The proposed full adder circuit is based on NAND and NOT logic gates. For this reason we characterize NAND and NOT gates at different supply voltages and frequencies, for both technologies. The optimal results, obtained using Advanced Design System (ADS), are at 0.5 V and 50 GHz for CNTFET, while for CMOS technology at 3 V and 200 MHz. Moreover we present the comparison between the two considered technologies in term of velocity, delay and power delay product (PDP), showing quantitatively the improvements obtained with CNTFET technology.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
