In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.
A model to improve analysis of CNTFET logic gates in verilog-A-part I: Static analysis
Marani R;
2015
Abstract
In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.File in questo prodotto:
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