Recent advances in high-speed acquisition of MR signals demand higher levels of performance from RF receiver chain. High-performance ADCs require a highly stable clock, in terms of short-term variations defined by the jitter specification. In this note, we propose a theory for the clock jitter influence estimation on the final image SNR. In particular, starting from a typical RF receiver chain design specification, that are required to obtain the desired SNR, we analyze the influence of the clock noise on the MR signal dynamic dividing the entire Offset Frequency Range (0-10MHz OFR) into two intervals according to different estimation methods. The obtained results show that, in our specific application, the jitter influence does not affect the final image SNR value. The presented methodology can be easily extended to every MR applications thanks to the high flexibility of the implemented concepts to use for choosing, in each case, the optimal oscillator with the wanted clock jitter, or to quantify the system performance degradation.
A theory for the estimation of SNR degradation caused by clock jitter in MRI systems
Hartwig V;Giovannetti G;Landini L;Benassi A
2007
Abstract
Recent advances in high-speed acquisition of MR signals demand higher levels of performance from RF receiver chain. High-performance ADCs require a highly stable clock, in terms of short-term variations defined by the jitter specification. In this note, we propose a theory for the clock jitter influence estimation on the final image SNR. In particular, starting from a typical RF receiver chain design specification, that are required to obtain the desired SNR, we analyze the influence of the clock noise on the MR signal dynamic dividing the entire Offset Frequency Range (0-10MHz OFR) into two intervals according to different estimation methods. The obtained results show that, in our specific application, the jitter influence does not affect the final image SNR value. The presented methodology can be easily extended to every MR applications thanks to the high flexibility of the implemented concepts to use for choosing, in each case, the optimal oscillator with the wanted clock jitter, or to quantify the system performance degradation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
