Computer graphics applications require efficient tools to model geometric objects. The traditional approach based on compute-intensive matrix calculations is error-prone due to a lack of integration between geometric reasoning and matrix-based algorithms. Clifford algebra offers a solution to these issues since it permits specification of geometry at a coordinate-free level. The best way to exploit the symbolic computing power of geometric (Clifford) algebra is supporting its data types and operators directly in hardware. This paper outlines the architecture of S-CliffoSor (Sliced Clifford coprocesSor), a parallelizable embedded coprocessor that executes native Clifford algebra operations. S-CliffoSor is a sliced coprocessor that can be replicated for parallel execution of concurrent Clifford operations. A single slice has been designed, implemented and tested on the Celoxica Inc. RC1000 board. The experimental results show the potential to achieve a 3x speedup for Clifford sums and 4x speedup for Clifford products compared to against the analogous operations in the software library generator GAIGEN. © 2007 IEEE.

A sliced coprocessor for native clifford algebra operations

Franchini S;
2007

Abstract

Computer graphics applications require efficient tools to model geometric objects. The traditional approach based on compute-intensive matrix calculations is error-prone due to a lack of integration between geometric reasoning and matrix-based algorithms. Clifford algebra offers a solution to these issues since it permits specification of geometry at a coordinate-free level. The best way to exploit the symbolic computing power of geometric (Clifford) algebra is supporting its data types and operators directly in hardware. This paper outlines the architecture of S-CliffoSor (Sliced Clifford coprocesSor), a parallelizable embedded coprocessor that executes native Clifford algebra operations. S-CliffoSor is a sliced coprocessor that can be replicated for parallel execution of concurrent Clifford operations. A single slice has been designed, implemented and tested on the Celoxica Inc. RC1000 board. The experimental results show the potential to achieve a 3x speedup for Clifford sums and 4x speedup for Clifford products compared to against the analogous operations in the software library generator GAIGEN. © 2007 IEEE.
2007
Inglese
Proceedings of the 10th IEEE Euromicro Conference on Digital System Design - Architectures, Methods and Tools (DSD 2007)
10th IEEE Euromicro Conference on Digital System Design - Architectures, Methods and Tools (DSD 2007)
436
439
076952978X
http://www.scopus.com/record/display.url?eid=2-s2.0-47749133415&origin=inward
IEEE Computer Society
Los Alamitos [CA]
STATI UNITI D'AMERICA
Sì, ma tipo non specificato
29-31 August, 2007
Lubeck, Germany
Clifford algebra
Embedded coprocessor
FPGA prototyping
1
none
Franchini, S.; Gentile, A.; Grimaudo, M.; Hung, C. A.; Impastato, S.; Sorbello, F.; Vassallo, G.; Vitabile, S.
273
info:eu-repo/semantics/conferenceObject
04 Contributo in convegno::04.01 Contributo in Atti di convegno
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/460416
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