A process for fabricating a device based on tunneling through a very thin vertical silicon membrane is presented. The process has been developed on a ?1 1 0? oriented silicon wafer using high resolution e-beam lithography and KOH anisotropic etching to define the structure. A single evaporation step allows the fabrication of both the source-drain contacts and a control gate self aligned to the top of the silicon membrane. A vertical silicon membrane with a thickness of 15 nm has been obtained.
A fabrication process for a silicon tunnel barrier with self aligned gate
M Piotto
2006
Abstract
A process for fabricating a device based on tunneling through a very thin vertical silicon membrane is presented. The process has been developed on a ?1 1 0? oriented silicon wafer using high resolution e-beam lithography and KOH anisotropic etching to define the structure. A single evaporation step allows the fabrication of both the source-drain contacts and a control gate self aligned to the top of the silicon membrane. A vertical silicon membrane with a thickness of 15 nm has been obtained.File in questo prodotto:
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