A comparison of hot-hole induced degradation in thin-film transistors using thermally recrystallised and LPCVD deposited polycrystalline silicon as active layer

In this work we have studied and compared the effects produced by prolonged application of bias-stresses with high source-drain voltage and negative gate voltages in two types of polysilicon thin-film transistors. Two main effects induced by bias-stressing have been observed: off-current reduction and transconductance degradation. The latter effect appears to be strongly related to gate leakage current which, in turns, is depending upon interface morphology.