Gate oxide reliability of Power MOSFETs strongly depends on their defectiveness levels. Higher defectiveness levels could involve in higher gate leakage current, threshold voltage shift effects and lower oxide reliability. Therefore, it is important to evaluate gate oxide defectiveness. This paper estimates the different oxide defectiveness levels of two main topologies utilized in Low Voltage Power MOSFETs and it shows how the Trench compared to the Planar oxide shows higher defectiveness levels especially considering interface traps. © VDE VERLAG GMBH · Berlin · Offenbach.

Gate oxide defectiveness levels: An experimental comparison between Planar and trench low voltage power MOSFET technologies

Consentino G.
2013

Abstract

Gate oxide reliability of Power MOSFETs strongly depends on their defectiveness levels. Higher defectiveness levels could involve in higher gate leakage current, threshold voltage shift effects and lower oxide reliability. Therefore, it is important to evaluate gate oxide defectiveness. This paper estimates the different oxide defectiveness levels of two main topologies utilized in Low Voltage Power MOSFETs and it shows how the Trench compared to the Planar oxide shows higher defectiveness levels especially considering interface traps. © VDE VERLAG GMBH · Berlin · Offenbach.
2013
Istituto per la Microelettronica e Microsistemi - IMM
978-3-8007-3505-1
Power MOSFETs
Characterization
Dielectric defectiveness level
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/520535
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