Design of a High-Performance Low-1/f-Noise Low-Dropout for Power Management Units

This article introduces an innovative, fully integrated low-dropout (LDO) specifically designed for low-power applications, capable of handling a wide range of load currents. By employing dynamic biasing to enhance noise performance, the LDO shows a noise equal to 14 (Formula presented.) at f < 1 kHz. The LDO demonstrates remarkable efficiency with a load regulation (LDR) of 3.8 mV/A and a line regulation (LNR) of 0.71 mV/V. It boasts a rapid settling time of 1 (Formula presented.) s during load transitions up to 100 mA and a minimal quiescent current of 5 (Formula presented.) A. The regulator consistently provides a 2.6 V output for input voltages between 2.8 V and 4.8 V, with a dropout voltage of 67 mV, supporting load currents from 0 mA to 100 mA over a temperature range of −25 °C to +125 °C. The design is based on a 150 nm CMOS process to ensure high sensitivity and high performance, making it an ideal choice for battery-operated systems.