Energy and power scaling in quantum computers based on rotated surface codes with silicon flip-flop qubits

Scalable solutions are essential to achieving the long-term goal of building a fault-tolerant quantum computer and energy-power consumption are fundamental limiting factors for this target. Among the available types of silicon qubits, this work focuses on Flip-Flop (FF) qubits. Energy consumption and power requirements are estimated for a square array of qubits that hosts the logical qubit. The logical qubit is implemented using the rotated Surface Code (SC) for Quantum Error Correction (QEC). By using a universal set of quantum gates, the energy usage, time and power requirements for a SC cycle are estimated based on noise level, code distance and control levels. These estimates are used to provide insights into the main scaling-up challenges for quantum computer development. This is achieved by extending a thermal model that includes energy contributions from both the cryogenic components (such as the qubit array, the cryogenic control electronics, and the cryostat) and the room temperature (RT) section (RT electronics and heat dissipation systems). The maximum numbers of physical and logical qubits are provided, as well as power consumption across the different temperature sections.