A FPGA Coprocessor for Accelerating Geometric Algebra Algorithms based on the GAPPCO Design

The high computational complexity of Geometric Algebra (GA) operations requires dedicated architectures to allow for their practical use in real-world applications. An integrated hardware-software system that exploits both the GAALOPWeb compiler and the GAPPCO coprocessor to accelerate GA algorithms is presented in this paper. GAPPCO is a reconfigurable coprocessor that can be programmed to support different GA algorithms. The GAPPCO coprocessor has been implemented as a System-on-Chip (SoC) on the Avnet Picozed development board containing both an ARM Cortex-A9 processor and a Xilinx Zynq-7000 FPGA device. A basic algorithm for the computation of a 5D vector reflection, which is the basis for all conformal geometric operations in Conformal Geometric Algebra (CGA), namely, rotations, translations, and dilations, has been used to test the effectiveness of the proposed approach. Preliminary results show that the integrated GAALOPWeb-GAPPCO system achieves average speedups of about 5× against the execution of the same algorithm on the standard ARM processor embedded in the Zynq-7000 chip.