Some devices, like LEDs and multi-junction solar cells, make use of thick III-V layers. Due to the different thermal expansion coefficients such thick layers undergo cracking and bowing that can cause device failure. This issue is more dramatic when the III-V layers are grown on Si to get monolithic integration of III-V optoelectronic devices onto Si microelectronic CMOS platforms. It was shown recently that cracking and bowing of thick Ge layers on Si do not occur by growing on deeply patterned Si, i.e. on Si pillars [1]. This approach was applied here to grow crack-free GaAs microcrystals on Si pillars. The type and arrangement of extended defects, that are still expected due to the lattice mismatch and polarity of the III-V deposit, in such novel structures are discussed in this work. The GaAs was grown on (001) Si 6° off to [110] at 580 °C by MBE at a rate of 0.5 ML/s with V/III=50. Prior to growth the Si substrate was patterned by deep reactive ion etching (DRIE), based on the Borsch process, into square-based pillars, 8 µm high and 5 or 9 µm wide. Defect analysis was performed by TEM operated in the two beam diffraction, High Resolution and High Angle Annular Dark Field modes. The GaAs was thicker than 2 µm and its top was defined by {113} and {111} facets. Both 60° and edge misfit dislocations formed at the GaAs/Si interface, as expected from the 4.2% lattice mismatch. Threading dislocations generated from them propagate up the GaAs only for ~500 nm due to their mutual interactions that left behind tiny dislocation loops. They thus do not reach the top of the GaAs microcrystal that will serve as active region in devices. Threading dislocations reach the top surface only at the lateral edges of the GaAs, again far from the active area. Twins were also observed that originate at the interface very likely at the steps of the offcut substrate. Contrary to the threading dislocations, twins reach the topmost part of GaAs. However, as twins have no associated dangling bonds, they should not be electrically active. Rare antiphase boundaries exist at the interface, hence not harmful for device operation. [1] C. V. Falub, H. von Kaenel, F. Isa, R. Bergamaschini, A. Marzegalli, D. Chrastina, G. Isella, E. Mueller, P. Niedermann, L. Miglio, Science 335, 1330 (2012)
A structural characterization of GaAs MBE grown on Si pillars
C Frigeri;
2013
Abstract
Some devices, like LEDs and multi-junction solar cells, make use of thick III-V layers. Due to the different thermal expansion coefficients such thick layers undergo cracking and bowing that can cause device failure. This issue is more dramatic when the III-V layers are grown on Si to get monolithic integration of III-V optoelectronic devices onto Si microelectronic CMOS platforms. It was shown recently that cracking and bowing of thick Ge layers on Si do not occur by growing on deeply patterned Si, i.e. on Si pillars [1]. This approach was applied here to grow crack-free GaAs microcrystals on Si pillars. The type and arrangement of extended defects, that are still expected due to the lattice mismatch and polarity of the III-V deposit, in such novel structures are discussed in this work. The GaAs was grown on (001) Si 6° off to [110] at 580 °C by MBE at a rate of 0.5 ML/s with V/III=50. Prior to growth the Si substrate was patterned by deep reactive ion etching (DRIE), based on the Borsch process, into square-based pillars, 8 µm high and 5 or 9 µm wide. Defect analysis was performed by TEM operated in the two beam diffraction, High Resolution and High Angle Annular Dark Field modes. The GaAs was thicker than 2 µm and its top was defined by {113} and {111} facets. Both 60° and edge misfit dislocations formed at the GaAs/Si interface, as expected from the 4.2% lattice mismatch. Threading dislocations generated from them propagate up the GaAs only for ~500 nm due to their mutual interactions that left behind tiny dislocation loops. They thus do not reach the top of the GaAs microcrystal that will serve as active region in devices. Threading dislocations reach the top surface only at the lateral edges of the GaAs, again far from the active area. Twins were also observed that originate at the interface very likely at the steps of the offcut substrate. Contrary to the threading dislocations, twins reach the topmost part of GaAs. However, as twins have no associated dangling bonds, they should not be electrically active. Rare antiphase boundaries exist at the interface, hence not harmful for device operation. [1] C. V. Falub, H. von Kaenel, F. Isa, R. Bergamaschini, A. Marzegalli, D. Chrastina, G. Isella, E. Mueller, P. Niedermann, L. Miglio, Science 335, 1330 (2012)I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
