Chalcogenide-based Phase Change Random Access Memories (PCRAM) are promising candidates for next generation non-volatile memory devices. GeSbTe (GST) alloys may ensure non-volatility, endurance, multiple bit operation, and very fast switching speed of the cells. But if from one side, it has been shown that PCRAM performance improves with the scaling of the cell, on the other hand, endurance seems to worse with scaling. In this scenario a detailed understanding of the structural and electrical properties of the material is crucial, particularly at the nanoscale level. Moreover, it would be desirable to have simplified structures, which allow access to the bits without the need of complete complex front-end and back-end processes in order to test at the nanoscale level with large statistics. To this end we propose a technique based on di-block copolymers lithography to produce dense arrays of amorphous islands of a few nanometers (10-20 nm) embedded in crystalline GST, in order to test the electrical properties of many bits in parallel with a sensitivity at the level of a few PCRAM cells. In this paper the technique to fabricate the nano-patterned GST films is detailed and the electrical behaviour of the nano-patterned GST is presented for different amorphization conditions, and compared to the planar case results.

Nano-patterning of GST thin films by self-assembled di-block copolymers lithography

Privitera S Privitera Stefania;
2007

Abstract

Chalcogenide-based Phase Change Random Access Memories (PCRAM) are promising candidates for next generation non-volatile memory devices. GeSbTe (GST) alloys may ensure non-volatility, endurance, multiple bit operation, and very fast switching speed of the cells. But if from one side, it has been shown that PCRAM performance improves with the scaling of the cell, on the other hand, endurance seems to worse with scaling. In this scenario a detailed understanding of the structural and electrical properties of the material is crucial, particularly at the nanoscale level. Moreover, it would be desirable to have simplified structures, which allow access to the bits without the need of complete complex front-end and back-end processes in order to test at the nanoscale level with large statistics. To this end we propose a technique based on di-block copolymers lithography to produce dense arrays of amorphous islands of a few nanometers (10-20 nm) embedded in crystalline GST, in order to test the electrical properties of many bits in parallel with a sensitivity at the level of a few PCRAM cells. In this paper the technique to fabricate the nano-patterned GST films is detailed and the electrical behaviour of the nano-patterned GST is presented for different amorphization conditions, and compared to the planar case results.
2007
Istituto per la Microelettronica e Microsistemi - IMM
978-1-55899-957-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/259524
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