We investigated the feasibility of electron programing and hole erasing in silicon nanocrystal Flash memory cells with fin field-effect transistor architecture having ultrashort channels (90 nm). Experiments show that, by choosing a proper program/erase condition, very large threshold voltage windows can be achieved, compatible with the needs of multilevel cells. These performances are coupled to excellent retention at high temperature. The obtained results evidence that hole trapping is less affected by electric field and temperature stress compared to electron trapping. Qualitative explanations for this behavior are given. (C) 2008 American Institute of Physics.
Electron programing and hole erasing in silicon nanocrystal Flash memories with fin field-effect transistor architecture
Corso D;Lombardo S;
2008
Abstract
We investigated the feasibility of electron programing and hole erasing in silicon nanocrystal Flash memory cells with fin field-effect transistor architecture having ultrashort channels (90 nm). Experiments show that, by choosing a proper program/erase condition, very large threshold voltage windows can be achieved, compatible with the needs of multilevel cells. These performances are coupled to excellent retention at high temperature. The obtained results evidence that hole trapping is less affected by electric field and temperature stress compared to electron trapping. Qualitative explanations for this behavior are given. (C) 2008 American Institute of Physics.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
