A three-power-level method for obtaining efficient thermo-optical modulation in an all-silicon waveguide-integrated Fabry-Perot thermo-optic modulator is discussed by means of a thermo-optical analytical model and demonstrated. The thermal system is represented as a two-pole model where, at every time, the temperature in the waveguide core is modified by means of a heater. This temperature is calculated and used in turn for calculating the refractive index. In this way, the impact of the driving signal shape on the device speed performance is assessed. Results clearly indicate that the application of a thermal bias holding the modulator at a higher average temperature with respect to the substrate heat sink allows increasing the modulator speed. An application-specific integrated circuit has been designed and developed in order to test the new modulation logic. The system's electronics is implemented in a 0.8 mu m, 5 V, CMOS process. The experimental results of this new three-power-level driver method are reported, showing the shortening of the characteristic transient times.

Modulation speed improvement in a Fabry-Perot thermo-optical modulator through a driving signal optimization technique

Della Corte FG;Iodice M;Rendina I;
2009

Abstract

A three-power-level method for obtaining efficient thermo-optical modulation in an all-silicon waveguide-integrated Fabry-Perot thermo-optic modulator is discussed by means of a thermo-optical analytical model and demonstrated. The thermal system is represented as a two-pole model where, at every time, the temperature in the waveguide core is modified by means of a heater. This temperature is calculated and used in turn for calculating the refractive index. In this way, the impact of the driving signal shape on the device speed performance is assessed. Results clearly indicate that the application of a thermal bias holding the modulator at a higher average temperature with respect to the substrate heat sink allows increasing the modulator speed. An application-specific integrated circuit has been designed and developed in order to test the new modulation logic. The system's electronics is implemented in a 0.8 mu m, 5 V, CMOS process. The experimental results of this new three-power-level driver method are reported, showing the shortening of the characteristic transient times.
2009
Istituto per la Microelettronica e Microsistemi - IMM
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/49760
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