An alternative method for the formation of the top oxide in oxide-nitride-oxide dielectric stacks is proposed. This method combines low-energy (1 keV) silicon ion implantation into a thin nitride-oxide stack and subsequent low-temperature wet oxidation (850 degrees C for 15 min). Transmission electron microscopy shows that for an implanted dose of 1.5x10(16) Si cm(-2), an 8-nm-thick silicon oxide layer develops on the surface of the nitride-oxide stack. Time of flight secondary ion mass spectrometry reveals: (1) transformation of the implanted silicon nitride to an oxygen-rich-silicon nitride layer and (2) pilling up of nitrogen atoms at the bottom silicon/oxide-substrate interface. The resulting oxide-nitride-oxide stack exhibits strong charge storage effects and excellent charge retention properties leading to a 1.5 V, 10 yr extrapolated memory window at 125 degrees C. These results suggest that the proposed fabrication route may lead to gate dielectric stacks of substantial potential impact for mainstream nitride-based memory devices. (c) 2007 American Institute of Physics.

Wet oxidation of nitride layer implanted with low-energy Si ions for improved oxide-nitride-oxide memory stacks

Perego M;Fanciulli M
2007

Abstract

An alternative method for the formation of the top oxide in oxide-nitride-oxide dielectric stacks is proposed. This method combines low-energy (1 keV) silicon ion implantation into a thin nitride-oxide stack and subsequent low-temperature wet oxidation (850 degrees C for 15 min). Transmission electron microscopy shows that for an implanted dose of 1.5x10(16) Si cm(-2), an 8-nm-thick silicon oxide layer develops on the surface of the nitride-oxide stack. Time of flight secondary ion mass spectrometry reveals: (1) transformation of the implanted silicon nitride to an oxygen-rich-silicon nitride layer and (2) pilling up of nitrogen atoms at the bottom silicon/oxide-substrate interface. The resulting oxide-nitride-oxide stack exhibits strong charge storage effects and excellent charge retention properties leading to a 1.5 V, 10 yr extrapolated memory window at 125 degrees C. These results suggest that the proposed fabrication route may lead to gate dielectric stacks of substantial potential impact for mainstream nitride-based memory devices. (c) 2007 American Institute of Physics.
2007
INFM
SI3N4
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/119083
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