Identification of Interface States responsible for VTH Hysteresis in packaged SiC MOSFETs

We investigate the mechanism governing threshold voltage (VTH) hysteresis in packaged SiC MOSFETs. A double-ramp measurement method was employed for this scope, being able to accurately evaluate the time-dependent recovery of the positive VTH shift induced by the sweep-up of the gate voltage. Particularly, we studied the effect of the (i) gate driving voltage (VGH), (ii) recovery time (TOFF) and (iii) temperature (T) on the VTH hysteresis. No appreciable differences were observed among data collected at different VGH, whereas a recovery speed-up was observed at higher T values. Temperature dependent measurement of VTH recovery yielded a 0.3 eV activation energy, that has been associated to SiC/SiO2 interface traps located ~0.3 eV below the SiC conduction band.