This work reports the realization and characterization of 4H-SiC p(+)/n diodes with the p(+) anodes made by Al+ ion implantation at 400 degrees C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6x10(19) cm(-3) and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600 degrees C to 1700 degrees C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 Omega-cm measured for the sample annealed at 1700 degrees C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased respectively, from 93% to 47% and from 2x10(-7) Acm(-2) to 1 x 10(-8) Acm(-2) at 100 V reverse bias, or increasing post implantation annealing temperature.
Ion Implanted p(+)/n diodes: post-implantation annealing in a silane ambient in a cold-wall low-pressure CVD reactor
Poggi;Antonella;Tamarri;Fabrizio;Nipoti;Roberta
2006
Abstract
This work reports the realization and characterization of 4H-SiC p(+)/n diodes with the p(+) anodes made by Al+ ion implantation at 400 degrees C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6x10(19) cm(-3) and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600 degrees C to 1700 degrees C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 Omega-cm measured for the sample annealed at 1700 degrees C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased respectively, from 93% to 47% and from 2x10(-7) Acm(-2) to 1 x 10(-8) Acm(-2) at 100 V reverse bias, or increasing post implantation annealing temperature.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


