The effect of nitrogen (N) introduced by ion implantation at the SiO(2)/4H-SiC interface on the capacitance of the MOS capacitors is investigated. The Thermal Dielectric Relaxation Current (TDRC) technique and Capacitance-Voltage (C-V) measurements performed at different temperatures and probe frequencies on an N implanted sample and on a virgin sample were employed for this purpose. There are three types of defects located at or near the interface, D(it), NIT(ox)(fast) and NIT(ox)(slow) that can be distinguished. Only D(it) and NIT(ox)(fast) respond to the a.c. small, high frequency signal at temperatures above 150K. The separation of D(it) from the NIT(ox)(fast) states have enabled us to study the influence of the excess of interfacial Nitrogen on each of the mentioned defects. It has been found that the N-implantation process fully suppresses the formation of NIT(ox)(fast) and partially NIT(ox)(slow) and D(it). Theoretical C-V characteristics were computed, based on the defect distributions determined by TDRC, and compared with the experimental ones showing a close agreement.

The influence of excess nitrogen, on the electrical properties of the 4H-SiC/SiO(2) interface

Moscatelli F;Nipoti R;Poggi A;Solmi S;
2011

Abstract

The effect of nitrogen (N) introduced by ion implantation at the SiO(2)/4H-SiC interface on the capacitance of the MOS capacitors is investigated. The Thermal Dielectric Relaxation Current (TDRC) technique and Capacitance-Voltage (C-V) measurements performed at different temperatures and probe frequencies on an N implanted sample and on a virgin sample were employed for this purpose. There are three types of defects located at or near the interface, D(it), NIT(ox)(fast) and NIT(ox)(slow) that can be distinguished. Only D(it) and NIT(ox)(fast) respond to the a.c. small, high frequency signal at temperatures above 150K. The separation of D(it) from the NIT(ox)(fast) states have enabled us to study the influence of the excess of interfacial Nitrogen on each of the mentioned defects. It has been found that the N-implantation process fully suppresses the formation of NIT(ox)(fast) and partially NIT(ox)(slow) and D(it). Theoretical C-V characteristics were computed, based on the defect distributions determined by TDRC, and compared with the experimental ones showing a close agreement.
2011
Istituto per la Microelettronica e Microsistemi - IMM
978-3-03785-079-4
n-MOS capacitors
N implantation
C-V
interface states
TDRC
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/275502
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