Comparative studies of gate oxides on a N+ pre-implanted area (N-interface similar to 1x10(19)cm(-3)) and on a virgin Si face 4H-SiC material (N-interface similar to 1x10(16)cm(-3)) have been undertaken by means of Capacitance-Voltage (C-V) characteristics, performed at different temperatures and frequencies, and Thermal Dielectric Relaxation Current technique. In the non implanted samples, the stretch out of the C-V curves get larger as the temperature is lowered to 150K, while for lower temperatures the C-V characteristics become steeper and some discontinuities occur. These discontinuities are specific for the non-implanted sample and are associated with charging of the fast near interface states (NIToxfast) via a tunneling from the shallow interface states (D-it). The tunneling from the shallow D-it to NIToxfast supress the a.c. response of D-it, which is recovered only after most of the NIToxfast are charged with electrons.

Non-nitridated oxides: abnormal behaviour of n-4H-SiC/SiO2 capacitors at low temperature caused by near interface states

Nipoti R;Poggi A;Solmi S;
2011-01-01

Abstract

Comparative studies of gate oxides on a N+ pre-implanted area (N-interface similar to 1x10(19)cm(-3)) and on a virgin Si face 4H-SiC material (N-interface similar to 1x10(16)cm(-3)) have been undertaken by means of Capacitance-Voltage (C-V) characteristics, performed at different temperatures and frequencies, and Thermal Dielectric Relaxation Current technique. In the non implanted samples, the stretch out of the C-V curves get larger as the temperature is lowered to 150K, while for lower temperatures the C-V characteristics become steeper and some discontinuities occur. These discontinuities are specific for the non-implanted sample and are associated with charging of the fast near interface states (NIToxfast) via a tunneling from the shallow interface states (D-it). The tunneling from the shallow D-it to NIToxfast supress the a.c. response of D-it, which is recovered only after most of the NIToxfast are charged with electrons.
2011
Istituto per la Microelettronica e Microsistemi - IMM
978-3-03785-079-4
SIC
n-MOS capacitors
N implantation
C-V
interface states
border traps
tunneling
TDRC
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.14243/275520
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus ND
  • ???jsp.display-item.citation.isi??? ND
social impact