Conduction Mechanisms at Interface of AIN/SiN Dielectric Stacks with AIGaN/GaN Heterostructures for Normally-off HEMTs: Correlating Device Behavior with Nanoscale Interfaces Properties

In this work, the conduction mechanisms at the interface of AIN/SiN dielectric stacks with AIGaN/GaN heterostructures have been studied combining different macroscopic and nanoscale characterizations on bare materials and devices. The AIN/SiN stacks grown on the recessed region of AIGaN/GaN heterostructures have been used as gate dielectric of hybrid metal-insulator-semiconductor high electron mobility transistors (MISHEMTs), showing a normally-off behavior (V-th = +1.2 V), high channel mobility (204 cm(2) V-1 s(-1)), and very good switching behavior (I-ON/I-OFF current ratio of (5-6) X 10(8) and subthreshold swing of 90 mV/dec). However, the transistors were found to suffer from a positive shift of the threshold voltage during subsequent bias sweeps, which indicates electron trapping in the dielectric stack. To get a complete understanding of the conduction mechanisms and of the charge trapping phenomena in AIN/SiN films, nanoscale current and capacitance measurements by conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been compared with a macroscopic temperature-dependent characterization of gate current in MIS capacitors. The nanoscale electrical analyses showed the presence of a spatially uniform distribution of electrons trapping states in the insulator and the occurrence of a density of 7 X 10(8) cm(-2) of local and isolated current spots at high bias values. These nanoscale conductive paths can be associated with electrically active defects responsible for the trap assisted current transport mechanism through the dielectric, observed by the temperature-dependent characterization of the gate current. The results of this study can be relevant for future applications of AIN/SiN bilayers in GaN hybrid MISHEMT technology.